What Is a Junction Field-Effect Transistor (JFET)?
A Junction Field-Effect Transistor (JFET) is a voltage-controlled semiconductor device that operates using the electric field effect.
A JFET has three terminals:
- Source (S)
- Drain (D)
- Gate (G)
The structure of a JFET can be explained using an N-channel JFET as an example.
In an N-channel JFET, two electrodes are connected to the ends of an N-type semiconductor material, serving as the Source and Drain. Two heavily doped P-type regions are formed on opposite sides of the N-type material and connected together to form the Gate. This creates two back-to-back PN junctions.
The N-type region through which current flows is called the channel, forming an N-channel JFET.
A P-channel JFET, on the other hand, uses a P-type semiconductor as its channel region.
Operating Principle of a JFET
A JFET controls current by varying the voltage between the Gate and Source (the reverse-bias voltage across the PN junction).
The depletion region of the PN junction expands into the more lightly doped semiconductor region, changing the effective cross-sectional area of the conductive channel and thereby controlling the current flow.
1. Zero Gate Bias: VGS = 0 V
There is no voltage difference between the gate and source, so the PN junction is at zero bias.
At this condition:
- The depletion region is at its narrowest.
- The N-type conductive channel is at its widest.
- The drain current (ID) reaches its maximum value (IDSS, the saturation drain current).
2. Negative Bias: Vp < VGS < 0 V
The PN junction becomes reverse-biased.
As a result:
- The depletion region widens.
- The conductive channel narrows.
- The drain current (ID) decreases.
By adjusting VGS, the drain current can be precisely controlled.
3. Pinch-Off: VGS ≤ Vp
When the reverse-bias voltage reaches the pinch-off voltage (Vp):
- The depletion region expands further.
- The channel becomes completely pinched off.
- Current flow is nearly cut off.
Advantages of JFETs
Conventional JFETs (long-channel JFETs) are not primarily valued for high voltage or high current capability. Instead, they offer several unique advantages.
1. Extremely High Input Impedance
The gate-to-channel junction is a reverse-biased PN junction.
Under normal operation:
- Gate current is virtually zero.
- Loading on the preceding circuit stage is extremely small.
2. Excellent Low-Noise Performance
JFETs are majority-carrier devices (conduction by electrons or holes).
As a result:
- They do not exhibit the surface carrier scattering noise associated with MOSFET channels.
- They generate very little shot noise compared to BJTs (Bipolar Junction Transistors).
This makes them ideal for low-noise amplification applications.
3. Good Linearity
Within the saturation (constant-current) region:
- Drain current exhibits an approximately square-law relationship with VGS.
- The transconductance (gm) changes relatively smoothly.
This makes JFETs well suited for high-quality analog signal processing.
4. Unipolar Device With No Secondary Breakdown
JFETs do not suffer from the secondary breakdown phenomenon commonly associated with BJTs, providing greater stability and reliability.
5. Strong Resistance to Electrostatic Discharge (ESD)
Because the gate structure is a PN junction:
- The depletion region is located inside the semiconductor.
- The structure is generally more robust than the thin gate oxide used in MOSFETs.
As a result, JFETs typically offer better ESD tolerance.
JFET Applications
Typical Long-Channel JFET Applications
1. High-Impedance Sensor Interfaces
Examples include:
- Piezoelectric sensors
- Capacitive microphone preamplifiers
2. High-Fidelity Audio Equipment
Examples include:
- Phono preamplifiers
- Microphone preamplifiers
- Audio mixer input stages
These applications take advantage of the JFET’s low-noise and high-linearity characteristics.
3. Analog Switches and Sample-and-Hold Circuits
Because JFETs offer:
- Simple control characteristics
- Low on-resistance
They can also be used to create simple and stable constant-current sources.
4. RF Circuits
JFETs are still widely used in certain:
- VHF (Very High Frequency)
- UHF (Ultra High Frequency)
low-noise amplifier designs.
Typical Short-Channel JFET Applications
Static Induction Transistors (SITs)
Short-channel JFET structures are commonly used in Static Induction Transistors (SITs).
Example: onsemi MMBFJ201
The onsemi MMBFJ201 can be used to illustrate JFET characteristics.
Key specifications include:
- N-channel JFET
- 40 V drain-source voltage rating
- Fully pinched off at approximately VGS = -1.5 V
The arrow in the N-channel JFET symbol indicates the direction that gate current would flow if gate current were present.
This condition should be avoided. In other words:
The PN junction formed between the gate and the channel should never be forward-biased during normal operation.
Limitations of JFETs
The MMBFJ201 datasheet illustrates one common drawback of JFETs:
Wide Parameter Variation
Parameters such as:
- Gate-source cutoff voltage (VGS(off))
- Saturation drain current (IDSS)
can vary significantly between devices and manufacturing lots.
JFET Operating Regions
The output characteristics of a JFET can be divided into:
- Linear Region
- Transition Region
- Saturation Region (Constant Current Region)
If VGS becomes excessive, operation may enter the:
- Avalanche Breakdown Region
where avalanche breakdown occurs across the PN junction.
Transfer characteristics also show that:
- At a fixed VGS,
- Drain current (ID) generally increases as temperature rises.
Design and Usage Considerations
Because N-channel devices use electrons as charge carriers:
- Electron mobility is higher.
- Switching and conduction characteristics are generally better.
- Manufacturing cost is typically lower.
For these reasons, N-channel JFETs are usually preferred in practical designs.
1. Avoid Forward-Biasing the Gate
- The gate-source PN junction normally operates under reverse bias.
- If the gate voltage exceeds approximately 0.6 V,
- The PN junction may become forward-biased.
- Excessive gate current may result.
2. Limit Gate Current
- Gate leakage current is typically in the nanoampere (nA) range.
- If forward bias cannot be avoided,
- A series current-limiting resistor should be used.
- A value of 100 kΩ or greater is recommended.
3. Observe ESD Precautions
Although JFETs are more robust than MOSFETs with respect to electrostatic discharge, their extremely high input impedance still requires careful handling.
Recommended precautions include:
- Avoid repeatedly soldering the same device.
- Ensure operators are properly grounded.
- Short all three terminals together before soldering.
- Avoid repeated rework operations.
- Never leave the gate terminal floating during testing.