Features
The MachXO2 breakout board (DigiKey Part number 220-2625-ND) is a low cost programmable logic device (PLD) development board. The MachXO2 is a low power FPGA with a hardened, ASIC-gate based, embedded function block (EFB). The following design topics will be covered:
• Peripheral expansion application introduction and overview
• Instantiation of the MachXO2 internal oscillator
• Using the embedded function block via the wishbone bus within the FPGA fabric
• Custom VHDL component design and instantiation to include a Button De-bouncer, Quadrature Encoder Interface (QEI), Gray Decoder, Wishbone Bus Control State Machine, and a Data Flow State Machine
• Hardware test modules for validation such as the Seven Segment Display (SSEG) Encoder and Display Multiplexer
Introduction
This reference design uses the MachXO2 low cost FPGA as an SPI based peripheral expansion device. In many applications such as industrial controls and consumer electronics, arrays of quadrature encoders, gray encoders, and tactile switches can be used as a human to machine interface. The main requirement of a design of this nature is heavy use of microcontroller/processor pins. Quadrature encoders are normally used with a special interface peripheral to track the position of an input knob with little to no processor overhead. Many microcontrollers/processors have limited encoder interfaces available. This reference design uses the machXO2 FPGA to take the input from 2 rotary encoders, one quadrature and one gray, and an array of buttons as an HMI to an ARM Cortex M3 device via SPI communication. What would normally take 14 pins is being handled with only 4. The inputs have been de-bounced to avoid hardware chatter; the buttons can also be de-bounced with RC filters to save on user logic. The gray encoder is optionally decoded to standard Hex. The design is perfectly scalable to include more input devices by instantiating more de-bouncer circuits, quadrature encoder interfaces, gray decoders, and tactile button arrays.
Background
The MachXO2 breakout board is a low-cost and low-power solution for many input and control applications. The EFB can save over 500 LUTs when implementing all of the EFB features in the provided hard ASIC gates in contrast to using the FPGA fabric. The Embedded Function Block includes the following hardened ASIC peripherals, as taken from the Lattice Technical Note TN1205:
• Two I2C cores
• One SPI core
• One 16-bit timer/counter
• User Flash Memory (MachXO2-640 and higher densities)
• Interface to Dynamic PLL configuration settings
• Interface to On-chip Power Controller through I2C and SPI
The Embedded Function Block’s Peripheral control is done through the use of the wishbone bus interface, a standard OpenCores compliant bus. This interface can be accessed through one of two master controls, either a LatticeMico8 or a custom state machine within the FPGA fabric. This reference design uses a state machine to control the wishbone bus and access the SPI. An additional state machine does the data manipulation and control, controlling the data path to the wishbone bus state machine. A system block level diagram can be seen below in figure 1.
Figure 1 MachXO2 SPI System Block-Level Diagram
Application
Building the Circuit
Instantiating the On Chip Oscillator and the Embedded Function Block (EFB)
To do this the MachXO2 library and package need to be invoked in the top level HDL wrapper file. Refer to the included top.vhd file to observe the application. It appears at the top of the top.vhd file as follows:
Library MACHXO2;
Use MACHXO2.components.all;
The component must be included between the top level architecture definition and the main description, this is also known as the declaration section. The nominal frequency can be defined in the component declaration and the instantiation within the Generic Map. This particular design is running at 38 MHz.
To instantiate the SPI peripheral within the EFB, IP express is used; this is executed by clicking on the IP express button within the Diamond tool bar. Select the EFB from the list of cores on the left to open the EFB configuration window as seen below in figure 2.
Figure 2 EFB Configuration Window
After the SPI settings have been configured the Generate button will create the HDL file for the SPI bus, interfaced through the wishbone bus. For details on this process, reference Lattice Technical Note TN1246, Using User Flash Memory and Hardened Control Functions in MachXO2 Devices Reference Guide.
Custom VHDL Component Design and Instantiation
This design includes a Button De-bouncer, Quadrature Encoder Interface (QEI), Gray Decoder, Wishbone Bus Control State Machine, and a Data Flow State Machine. The button de-bouncer works as a time-based filter to update an output depending on the longevity of an input. The button de-bouncer is more critical for circuits that count how many times an input might occur. The QEI module benefits from the de-bounce circuit by not counting erroneous inputs created from mechanical chatter within the encoder. The QEI keeps track of the knob position through the use of a two channel out-of-phase input. The phase difference in the two channels is used to increment or decrement a counter. The module also has the ability to track how far the knob has been turned over a constant time period for velocity applications; this functionality has been commented out of the module for this design. The Gray Decoder is simply a quick method to convert a gray code progression to a standard sequential hex progression dependant on the position of the gray code knob. The Wishbone Bus Control and Data Flow State Machines are two of the more complicated components in the design. To fully understand how aforementioned state machines operate with the wishbone bus, reference Lattice TN1246 to learn about the wishbone read and write signaling and associated timing.
The state flow diagrams for the wishbone bus control and data flow state machines can be seen below in figures 3 and 4 respectively.
Figure 3 Wishbone Control State Machine State Diagram
Figure 4 SPI Data Flow State Machine
Hardware Test Modules
Several components were used in this design to validate the values held in each of the input registers. This was done by displaying the values on an external seven segment display and an array of LEDs on the breakout board. The most significant nibbles on the SSEG display show the address sent by the SPI master to the MachXO2. The two least significant nibbles display the position of the quadrature encoder taken from a register within the MachXO2. The on-board LEDs display the output from the gray-to-hex decoder. In order to operate the SSEG display, several supporting components were used such as the Hex to SSEG Display Encoder and Display Multiplexer. These components are used to control the data going to the display and the switching for the anodes. The display is refreshed at around 190 Hz via a 17 bit timer. The seven segment display can be seen in figure 5 below.
Figure 5 Seven Segment Display Used for SPI Verification
Notice how the Arm Cortex M3 (SPI master) data displayed on the OLED screen (seen below in figure 6) matches the data on the SSEG display coming from the MachXO2 (SPI slave), seen in figure 5 above. The busy signal from the wishbone control state machine has also been routed externally for observation via pin 142.
Figure 6 Arm Cortex M3 OLED Data Matches FPGA SSEG Display Data
The VHDL component hierarchy can be seen below in figure 7. This was generated within Diamond by clicking the Generate Hierarchy button in the Diamond tool bar.
Figure 7 MachXO2 SPI Peripheral Expansion Hierarchy
Capabilities, Limitations, and Alterations
Lattice Diamond version 1.4.2.105 was used to develop this reference design with supporting software from Synopsis (Synplify Pro) and Aldec (Active HDL 8.3 Lattice WEB Edition II). Lattice Diamond can be used as a stand alone development environment with third party synthesis and simulation software.
Conclusion
This reference design illustrates how one can use the MachXO2 as a method of peripheral expansion. With an array of eight quadrature encoders, two gray encoders, and eight buttons, the effective processor IO utilized pin count can be reduced from 32 pins down to only 4, for SPI communication.
Additional Information
Further design support, product tutorials, application notes, user’s guides and other documentation can be found on the Lattice website at: http://www.latticesemi.com/dynamic/index.cfm?fuseaction=view_category&source=topnav
Appendix: Download
The complete, MachXO2 SPI Peripheral Expansion for HMI Applications, VHDL files can be downloaded here.
SPI_Peripheral_Expansion.zip (779.2 KB)