Series-Connected Silicon Carbide (SiC) MOSFETs - Passive Voltage Balancing Using RCD Snubbers
This post is based on the application note “Series-Connected Silicon Carbide MOSFETs: Passive Voltage Balancing Using RCD Snubbers”.
The app note discusses how SiC MOSFETs can be connected in series to create a higher-voltage power switch.
The main challenge is ensuring that the total stack voltage divides safely across all MOSFETs.
The focus is on passive voltage balancing using RCD snubbers for dynamic sharing and balancing resistors for static sharing.
The app note highlights the key operating principles, practical design considerations for balancing the stack, measurement concerns and experimental validation results.
Why Put SiC MOSFETs in Series?
Series stacking allows lower-voltage SiC MOSFETs to operate as one higher-voltage switch.
Expands device selection instead of relying only on very high-voltage discrete devices.
Can reduce overall cost by using more readily available, lower-voltage devices instead of expensive high-voltage parts.
Useful for higher DC bus and medium-voltage converter designs.
The stack must be driven and validated as one controlled high-voltage switch.
The Core Problem: Voltage Sharing Is Not Automatic
Series current is common, so current sharing is not the main issue.
The total stack voltage must be divided safely across each MOSFET.
Mismatch can overstress one device even when the total bus voltage is within the combined rating.
Static and dynamic imbalances need different mitigation paths.
The RCD Snubber Concept
RCD snubbers offer simple, passive voltage balancing; no sensing or control needed.
Modular approach: each MOSFET has its own adjustable snubber for better VDS sharing.
Csnub adds controlled capacitance across the MOSFET.
Dsnub provides a low-impedance charging path during VDS rise.
Rsnub resets the capacitor and dissipates stored energy before the next event.
The branch slows down and shapes the turn-off voltage rise.
Static vs. Dynamic Voltage Imbalance
Why Static Resistors Cannot Fix Fast Turn-Off Imbalance
Turn-off VDS rise happens on a much faster time scale than resistor equalization.
Rbal is intentionally large to limit standing loss.
The resistor cannot rapidly redistribute charge during the switching edge.
Dynamic sharing must be controlled by the capacitance and current paths active during VDS rise.
Dynamic Voltage Sharing: Match dVDS/dt, Not Csnub
During turn-off, each device VDS rise is set by its local effective current and effective capacitance.
The key relationship is: dVDS/dt ≈ ieff / Ceq
Ceq includes Coss, Csnub, layout/package capacitance, heatsink coupling, gate-driver isolation capacitance, and probe capacitance.
ieff and Ceq can be different for each MOSFET position in the series stack.
After confirming the VGS waveforms are aligned, the dynamic-balancing goal is to make all VDS rise rates match.
Equal dVDS/dt may require unequal Csnub values tuned by MOSFET position.
The final objective is not equal snubber values. Rather, it is equal VDS rise rates and balanced device voltages.
Turn-Off Operation: How RCD Snubbers Balance VDS
Measurement Setup: Be Careful What the Probes Change
High-voltage differential probes add capacitance and common-mode current paths.
Simultaneous probing can change the measured voltage distribution.
Preferred reference: measure each VDS individually with other probes removed.
Deskew probes before timing comparisons or snubber tuning.
Practical Design Flow
Validate at worst-case turn-off current because it usually gives the highest VDS slew rate and displacement-current sensitivity.
Do not tune snubbers until the measurement setup is deskewed and gate timing is aligned.
After changing Csnub, re-check reset time, resistor loss, diode stress and capacitor RMS/pulse capability.
How to Diagnose and Tune Imbalance
Start from equal or calculated initial snubber values.
Measure individual VDS waveforms with the least intrusive setup practical.
Identify which MOSFET rises fastest or reaches the highest voltage.
Increase Csnub for a device that rises too fast or reaches excessive VDS. Decrease Csnub for a device that rises too slow.
Iterate until VDS rise rates and final blocking voltages are close.
Experimental Platform
| Parameter | Value/Description |
|---|---|
| Converter topology | Buck converter |
| Nominal input voltage (Vin) | 2000 VDC |
| Nominal output voltage (Vout) | 400 VDC |
| Output power (Pout) | 500W |
| Switching frequency (fsw) | 50 kHz |
| Output inductor (Lout) | 6 mH (using an off-board inductor bank) |
| Output capacitance (Cout) | 110 µF |
| Buck main switch | Four series-connected 700 V, 60 mΩ SiC MOSFETs (Microchip MSC060SMA070B4N) |
| Freewheeling diode | 3.3 kV Microchip SiC diode |
| (Microchip MSC030SDA330B) | |
| Ideal off-state voltage per MOSFET | 500V at 2000 V bus |
| Dynamic balancing network | RCD snubber across each MOSFET |
| Static balancing network | Balancing resistor across each MOSFET |
Key Result: Equal 660 pF Snubbers Were Not Enough
Key Result: Tuned RCD Snubbers Balanced the Stack
Parasitics and Probes Can Change the Voltage Balancing
Every added capacitance creates a high-dv/dt displacement-current path.
Unified grounded heatsink produced the largest voltage spread in the equal-snubber tests.
Increasing gate-driver isolated supply capacitance increased ΔVDS,max.
Measurement setup, heatsink and driver supply must be treated as part of the voltage-sharing design.
Tuned RCD Snubbers: Voltage-Sharing Improvement
Tuned capacitors intentionally used different values by MOSFET position.
Across four configurations, ΔVDS,max dropped by approximately 85% to 94%.
Maximum device stress also decreased, improving the voltage margin of the worst-case MOSFET.
Tuning compensates for position-dependent parasitics and displacement-current behavior.
Final Takeaways
Series stacking increases voltage capability, but voltage sharing becomes the key design challenge.
RCD snubbers control fast dynamic voltage sharing during turn-off.
Equal gate timing and equal snubber values are necessary starting points, but they do not guarantee balanced VDS.
Parasitics matter: heatsink coupling, gate-driver isolation capacitance, layout and probes can shift voltage sharing.
Equal snubber values are a starting point, not a final design rule.
Position-dependent snubber tuning may be needed to make the VDS rise rates and final blocking voltages match.
Final validation should be based on measured VDS spread, maximum device stress, snubber loss and component temperature at worst-case conditions.