The following demo assumes that the Altera Quartus Software is properly installed per our previous article. This simple demo will display an internal counter sequence in the LED’s and a fixed data on the 7 Segment Display on the DE-25 FPGA Dev Kit,
Please create the project directory for this demo for the following files for the DE-25 FPGA Dev Kit,
top.sdc
top.tcl
top.v
\output_files
The top.sdc file for this demo is,
# DigiKey Coffee Cup .sdc file
#**************************************************************
# Create Clock
#**************************************************************
# CLOCK
create_clock -period "50MHz" [get_ports CLOCK0_50]
#**************************************************************
# Create Generated Clock
#**************************************************************
derive_pll_clocks
#**************************************************************
# Set Clock Uncertainty
#**************************************************************
derive_clock_uncertainty
Also create the following file called top.tcl
package require ::quartus::project
set need_to_close_project 0
set make_assignments 1
if {[is_project_open]} {
if {[string compare $quartus(project) "top"]} {
puts "Project top is not open"
set make_assignments 0
}
} else {
if {[project_exists top]} {
project_open -revision top top
} else {
project_new -revision top top
}
set need_to_close_project 1
}
if {$make_assignments} {
set_global_assignment -name FAMILY "Agilex 5"
set_global_assignment -name DEVICE A5ED013BB32AE4SCS
set_global_assignment -name TOP_LEVEL_ENTITY top
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "25.1.0 PRO EDITION"
set_global_assignment -name LAST_QUARTUS_VERSION "25.3.1 Pro Edition"
set_global_assignment -name DEVICE_FILTER_PACKAGE VPBGA
set_global_assignment -name USE_CONF_DONE SDM_IO16
set_global_assignment -name USE_HPS_COLD_RESET SDM_IO11
set_global_assignment -name USE_INIT_DONE SDM_IO13
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "ACTIVE SERIAL X4"
set_global_assignment -name ACTIVE_SERIAL_CLOCK AS_FREQ_100MHZ
set_global_assignment -name DEVICE_INITIALIZATION_CLOCK OSC_CLK_1_125MHZ
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name VERILOG_FILE top.v
set_global_assignment -name SDC_FILE top.sdc
set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "LINEAR FORMAT"
set_global_assignment -name PWRMGT_LINEAR_FORMAT_N "-12"
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CLOCK0_50 -entity top
set_location_assignment PIN_CH128 -to CLOCK0_50
set_instance_assignment -name IO_STANDARD "1.2-V" -to CPU_RESET_n -entity top
set_instance_assignment -name IO_STANDARD "1.2-V" -to KEY[0] -entity top
set_instance_assignment -name IO_STANDARD "1.2-V" -to KEY[1] -entity top
set_instance_assignment -name IO_STANDARD "1.2-V" -to KEY[2] -entity top
set_instance_assignment -name IO_STANDARD "1.2-V" -to KEY[3] -entity top
set_location_assignment PIN_BM78 -to CPU_RESET_n
set_location_assignment PIN_BW59 -to KEY[0]
set_location_assignment PIN_CA59 -to KEY[1]
set_location_assignment PIN_CF71 -to KEY[2]
set_location_assignment PIN_CH71 -to KEY[3]
set_instance_assignment -name IO_STANDARD "1.2-V" -to SW[0] -entity top
set_instance_assignment -name IO_STANDARD "1.2-V" -to SW[1] -entity top
set_instance_assignment -name IO_STANDARD "1.2-V" -to SW[2] -entity top
set_instance_assignment -name IO_STANDARD "1.2-V" -to SW[3] -entity top
set_instance_assignment -name IO_STANDARD "1.2-V" -to SW[4] -entity top
set_instance_assignment -name IO_STANDARD "1.2-V" -to SW[5] -entity top
set_instance_assignment -name IO_STANDARD "1.2-V" -to SW[6] -entity top
set_instance_assignment -name IO_STANDARD "1.2-V" -to SW[7] -entity top
set_instance_assignment -name IO_STANDARD "1.2-V" -to SW[8] -entity top
set_instance_assignment -name IO_STANDARD "1.2-V" -to SW[9] -entity top
set_location_assignment PIN_BM62 -to SW[0]
set_location_assignment PIN_BP62 -to SW[1]
set_location_assignment PIN_BH62 -to SW[2]
set_location_assignment PIN_BH59 -to SW[3]
set_location_assignment PIN_BM59 -to SW[4]
set_location_assignment PIN_BK59 -to SW[5]
set_location_assignment PIN_BU62 -to SW[6]
set_location_assignment PIN_CF59 -to SW[7]
set_location_assignment PIN_BU59 -to SW[8]
set_location_assignment PIN_BR59 -to SW[9]
set_instance_assignment -name IO_STANDARD "1.2-V" -to LEDR[0] -entity top
set_instance_assignment -name IO_STANDARD "1.2-V" -to LEDR[1] -entity top
set_instance_assignment -name IO_STANDARD "1.2-V" -to LEDR[2] -entity top
set_instance_assignment -name IO_STANDARD "1.2-V" -to LEDR[3] -entity top
set_instance_assignment -name IO_STANDARD "1.2-V" -to LEDR[4] -entity top
set_instance_assignment -name IO_STANDARD "1.2-V" -to LEDR[5] -entity top
set_instance_assignment -name IO_STANDARD "1.2-V" -to LEDR[6] -entity top
set_instance_assignment -name IO_STANDARD "1.2-V" -to LEDR[7] -entity top
set_instance_assignment -name IO_STANDARD "1.2-V" -to LEDR[8] -entity top
set_instance_assignment -name IO_STANDARD "1.2-V" -to LEDR[9] -entity top
set_location_assignment PIN_CC71 -to LEDR[0]
set_location_assignment PIN_BH78 -to LEDR[1]
set_location_assignment PIN_CH69 -to LEDR[2]
set_location_assignment PIN_CF69 -to LEDR[3]
set_location_assignment PIN_CA62 -to LEDR[4]
set_location_assignment PIN_CC62 -to LEDR[5]
set_location_assignment PIN_CF62 -to LEDR[6]
set_location_assignment PIN_BM69 -to LEDR[7]
set_location_assignment PIN_CA71 -to LEDR[8]
set_location_assignment PIN_BR62 -to LEDR[9]
set_instance_assignment -name IO_STANDARD "1.2-V" -to HEX0[0] -entity top
set_instance_assignment -name IO_STANDARD "1.2-V" -to HEX0[1] -entity top
set_instance_assignment -name IO_STANDARD "1.2-V" -to HEX0[2] -entity top
set_instance_assignment -name IO_STANDARD "1.2-V" -to HEX0[3] -entity top
set_instance_assignment -name IO_STANDARD "1.2-V" -to HEX0[4] -entity top
set_instance_assignment -name IO_STANDARD "1.2-V" -to HEX0[5] -entity top
set_instance_assignment -name IO_STANDARD "1.2-V" -to HEX0[6] -entity top
set_instance_assignment -name IO_STANDARD "1.2-V" -to HEX1[0] -entity top
set_instance_assignment -name IO_STANDARD "1.2-V" -to HEX1[1] -entity top
set_instance_assignment -name IO_STANDARD "1.2-V" -to HEX1[2] -entity top
set_instance_assignment -name IO_STANDARD "1.2-V" -to HEX1[3] -entity top
set_instance_assignment -name IO_STANDARD "1.2-V" -to HEX1[4] -entity top
set_instance_assignment -name IO_STANDARD "1.2-V" -to HEX1[5] -entity top
set_instance_assignment -name IO_STANDARD "1.2-V" -to HEX1[6] -entity top
set_instance_assignment -name IO_STANDARD "1.2-V" -to HEX2[0] -entity top
set_instance_assignment -name IO_STANDARD "1.2-V" -to HEX2[1] -entity top
set_instance_assignment -name IO_STANDARD "1.2-V" -to HEX2[2] -entity top
set_instance_assignment -name IO_STANDARD "1.2-V" -to HEX2[3] -entity top
set_instance_assignment -name IO_STANDARD "1.2-V" -to HEX2[4] -entity top
set_instance_assignment -name IO_STANDARD "1.2-V" -to HEX2[5] -entity top
set_instance_assignment -name IO_STANDARD "1.2-V" -to HEX2[6] -entity top
set_instance_assignment -name IO_STANDARD "1.2-V" -to HEX3[0] -entity top
set_instance_assignment -name IO_STANDARD "1.2-V" -to HEX3[1] -entity top
set_instance_assignment -name IO_STANDARD "1.2-V" -to HEX3[2] -entity top
set_instance_assignment -name IO_STANDARD "1.2-V" -to HEX3[3] -entity top
set_instance_assignment -name IO_STANDARD "1.2-V" -to HEX3[4] -entity top
set_instance_assignment -name IO_STANDARD "1.2-V" -to HEX3[5] -entity top
set_instance_assignment -name IO_STANDARD "1.2-V" -to HEX3[6] -entity top
set_instance_assignment -name IO_STANDARD "1.2-V" -to HEX4[0] -entity top
set_instance_assignment -name IO_STANDARD "1.2-V" -to HEX4[1] -entity top
set_instance_assignment -name IO_STANDARD "1.2-V" -to HEX4[2] -entity top
set_instance_assignment -name IO_STANDARD "1.2-V" -to HEX4[3] -entity top
set_instance_assignment -name IO_STANDARD "1.2-V" -to HEX4[4] -entity top
set_instance_assignment -name IO_STANDARD "1.2-V" -to HEX4[5] -entity top
set_instance_assignment -name IO_STANDARD "1.2-V" -to HEX4[6] -entity top
set_instance_assignment -name IO_STANDARD "1.2-V" -to HEX5[0] -entity top
set_instance_assignment -name IO_STANDARD "1.2-V" -to HEX5[1] -entity top
set_instance_assignment -name IO_STANDARD "1.2-V" -to HEX5[2] -entity top
set_instance_assignment -name IO_STANDARD "1.2-V" -to HEX5[3] -entity top
set_instance_assignment -name IO_STANDARD "1.2-V" -to HEX5[4] -entity top
set_instance_assignment -name IO_STANDARD "1.2-V" -to HEX5[5] -entity top
set_instance_assignment -name IO_STANDARD "1.2-V" -to HEX5[6] -entity top
set_location_assignment PIN_BP81 -to HEX0[0]
set_location_assignment PIN_BM81 -to HEX0[1]
set_location_assignment PIN_BM89 -to HEX0[2]
set_location_assignment PIN_BK89 -to HEX0[3]
set_location_assignment PIN_BH92 -to HEX0[4]
set_location_assignment PIN_BM92 -to HEX0[5]
set_location_assignment PIN_BP92 -to HEX0[6]
set_location_assignment PIN_CA78 -to HEX1[0]
set_location_assignment PIN_BW78 -to HEX1[1]
set_location_assignment PIN_BU78 -to HEX1[2]
set_location_assignment PIN_BR78 -to HEX1[3]
set_location_assignment PIN_BU81 -to HEX1[4]
set_location_assignment PIN_BR81 -to HEX1[5]
set_location_assignment PIN_CA89 -to HEX1[6]
set_location_assignment PIN_BW89 -to HEX2[0]
set_location_assignment PIN_BU92 -to HEX2[1]
set_location_assignment PIN_BR92 -to HEX2[2]
set_location_assignment PIN_BU89 -to HEX2[3]
set_location_assignment PIN_BR89 -to HEX2[4]
set_location_assignment PIN_CF78 -to HEX2[5]
set_location_assignment PIN_CH78 -to HEX2[6]
set_location_assignment PIN_CC81 -to HEX3[0]
set_location_assignment PIN_CA81 -to HEX3[1]
set_location_assignment PIN_CH81 -to HEX3[2]
set_location_assignment PIN_CF81 -to HEX3[3]
set_location_assignment PIN_CF89 -to HEX3[4]
set_location_assignment PIN_CH89 -to HEX3[5]
set_location_assignment PIN_CH92 -to HEX3[6]
set_location_assignment PIN_CF92 -to HEX4[0]
set_location_assignment PIN_CA92 -to HEX4[1]
set_location_assignment PIN_CC92 -to HEX4[2]
set_location_assignment PIN_CL76 -to HEX4[3]
set_location_assignment PIN_CK76 -to HEX4[4]
set_location_assignment PIN_CL82 -to HEX4[5]
set_location_assignment PIN_CK80 -to HEX4[6]
set_location_assignment PIN_CL85 -to HEX5[0]
set_location_assignment PIN_CK85 -to HEX5[1]
set_location_assignment PIN_BK69 -to HEX5[2]
set_location_assignment PIN_BP71 -to HEX5[3]
set_location_assignment PIN_BH89 -to HEX5[4]
set_location_assignment PIN_BH71 -to HEX5[5]
set_location_assignment PIN_CH62 -to HEX5[6]
set_global_assignment -name FLOW_ENABLE_DESIGN_ASSISTANT ON -family "Agilex 5"
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON -family "Agilex 5"
set_global_assignment -name TDC_CCPP_TRADEOFF_TOLERANCE 0 -family "Agilex 5"
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL ON -family "Agilex 5"
set_global_assignment -name ALLOW_RAM_RETIMING ON -family "Agilex 5"
set_global_assignment -name ALLOW_DSP_RETIMING ON -family "Agilex 5"
set_global_assignment -name AUTO_OPEN_DRAIN_PINS OFF -family "Agilex 5"
set_global_assignment -name PHYSICAL_SHIFT_REGISTER_INFERENCE ON -family "Agilex 5"
set_global_assignment -name MAXIMUM_SYNCHRONIZER_LENGTH_PROTECTED 3 -family "Agilex 5"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM ON -family "Agilex 5"
set_global_assignment -name ADVANCED_PHYSICAL_SYNTHESIS_REGISTER_PACKING ON -family "Agilex 5"
set_global_assignment -name PHYSICAL_SYNTHESIS ON -family "Agilex 5"
set_global_assignment -name POST_ROUTE_PHYSICAL_SYNTHESIS ON -family "Agilex 5"
set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -family "Agilex 5"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS" -family "Agilex 5"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON -family "Agilex 5"
set_global_assignment -name ENABLE_PHYSICAL_DSP_MERGING ON -family "Agilex 5"
set_global_assignment -name AUTO_DELAY_CHAINS ON -family "Agilex 5"
set_global_assignment -name ENABLE_ED_CRC_CHECK ON -family "Agilex 5"
set_global_assignment -name ALLOW_SEU_FAULT_INJECTION OFF -family "Agilex 5"
set_global_assignment -name FITTER_RESYNTHESIS ON -family "Agilex 5"
set_global_assignment -name FITTER_EARLY_RETIMING ON -family "Agilex 5"
set_global_assignment -name ENABLE_TIME_BORROWING_OPTIMIZATION ON -family "Agilex 5"
set_global_assignment -name FLOW_ENABLE_HYPER_RETIMER_FAST_FORWARD OFF -family "Agilex 5"
set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ON_HIERARCHY ON -family "Agilex 5"
set_global_assignment -name GENERATE_PR_RBF_FILE ON -family "Agilex 5"
set_global_assignment -name HPS_INITIALIZATION "AFTER INIT_DONE" -family "Agilex 5"
set_global_assignment -name PROGRAMMING_BITSTREAM_ENCRYPTION_KEY_SELECT "Battery Backup RAM" -family "Agilex 5"
set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS MAXIMUM -family "Agilex 5"
export_assignments
if {$need_to_close_project} {
project_close
}
}
Finally create the top.v for this project as,
//DigiKey Coffee Cup Top Module for the Demo
module top(
input CLOCK0_50,
input CPU_RESET_n,
input [ 3: 0] KEY,
input [ 9: 0] SW,
output [ 9: 0] LEDR,
output [ 6: 0] HEX0,
output [ 6: 0] HEX1,
output [ 6: 0] HEX2,
output [ 6: 0] HEX3,
output [ 6: 0] HEX4,
output [ 6: 0] HEX5
);
//LED COUNTER DEMO
reg [31:0] counter;
initial begin
counter = 0;
end
always @(posedge CLOCK0_50)
begin
counter <= counter + 1;
end
assign LEDR[0] = counter[28];
assign LEDR[1] = counter[27];
assign LEDR[2] = counter[26];
assign LEDR[3] = counter[25];
assign LEDR[4] = counter[24];
assign LEDR[5] = counter[23];
assign LEDR[6] = counter[22];
assign LEDR[7] = counter[21];
assign LEDR[8] = counter[20];
assign LEDR[9] = counter[19];
//STATIC DATE FOR 7 SEGMENT DISPLAY DEMO
//6
assign HEX0[0] = 0;
assign HEX0[1] = 1;
assign HEX0[2] = 0;
assign HEX0[3] = 0;
assign HEX0[4] = 0;
assign HEX0[5] = 0;
assign HEX0[6] = 0;
//2
assign HEX1[0] = 0;
assign HEX1[1] = 0;
assign HEX1[2] = 1;
assign HEX1[3] = 0;
assign HEX1[4] = 0;
assign HEX1[5] = 1;
assign HEX1[6] = 0;
//6
assign HEX2[0] = 0;
assign HEX2[1] = 1;
assign HEX2[2] = 0;
assign HEX2[3] = 0;
assign HEX2[4] = 0;
assign HEX2[5] = 0;
assign HEX2[6] = 0;
//0
assign HEX3[0] = 0;
assign HEX3[1] = 0;
assign HEX3[2] = 0;
assign HEX3[3] = 0;
assign HEX3[4] = 0;
assign HEX3[5] = 0;
assign HEX3[6] = 1;
//2
assign HEX4[0] = 0;
assign HEX4[1] = 0;
assign HEX4[2] = 1;
assign HEX4[3] = 0;
assign HEX4[4] = 0;
assign HEX4[5] = 1;
assign HEX4[6] = 0;
//0
assign HEX5[0] = 0;
assign HEX5[1] = 0;
assign HEX5[2] = 0;
assign HEX5[3] = 0;
assign HEX5[4] = 0;
assign HEX5[5] = 0;
assign HEX5[6] = 1;
endmodule
In order to build this project proceed to issue the following command,
# quartus_sh -t top.tcl
then proceed to compile the design as follows,
# quartus_sh --flow compile top
Finally program DE-25 FPGA Dev Kit with this demo,
# quartus_pgm -m jtag -o "p;output_files/top.sof"
The following video shows this demo for the DE-25 FPGA Dev Kit,
This video shows the counting sequence on the LEDs and also a fixed date as today’s date 020626 on the old school 7 Segment Display. This completes this simple demo for the DE-25 FPGA Dev Kit,.
The DE-25 FPGA Dev Kit, featuring an Agilex 5 is very user friendly like many of the classical boards and is available at DigiKey.
Have a nice day!
This article is available in spanish here.
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