The Lattice ICE40 UltraPlus Breakout Board is an excellent entry level FPGA development board but yet very powerful for many applications with an ICE40UP5K FPGA with a 1.2 V core supply.
The Lattice ICE40 UltraPlus Breakout Board has the following features,
ICE40 UltraPlus (iCE40UP5K-SG48) device in a 48-PIN QFN package.
— Example of a board using this 0.5mm pitch QFN package.
— High-current RGB LED output
— iCE40 UltraPlus Current Measurements
— Standard USB cable for device programming.
— RoHS-compliant packaging and process
The Lattice ICE40 UltraPlus Breakout Board allows for programming of the iCE40 UltraPlus or the SPI Flash:
SPI Flash Programming J6 shunt pins 1-3 and 2-4 (Default shunted)
— U5 Micron Technology Inc. part number N25Q032A13ESC40F
iCE40 UltraPlus Configuration or Programming J6 shunt pins 1-2 and 3-4
— U1 iCE40UP5K – SG48
CRESETB can be asserted by pushing SW1
— Can be probed with J11
Done LED D2
— Can be probed with J28 (Default shunted)
The block diagram of the Lattice ICE40 UltraPlus Breakout Board is shown below,
The first demo for this board is to develop a simple verilog HDL to interconnect the Switches directly to the RGB led on the board. There are three typical ways to do this, one is via the Lattice Development avenue, another one is via the open source Project IceStorm or via a very simple classical APIO mechanism which has been covered many times before.
Here we will cover the Project IceStorm and the APIO mechanisms. This demo will be developed in a Linux host that is connected via the USB cable of the Lattice ICE40 UltraPlus Breakout Board. For the Project IceStorm the installation process for this as follows,
sudo apt install yosys nextpnr-ice40 fpga-icestorm
The verilog HDL code relevant to this demo is leds.v
module top(input [3:0] SW, output LED_R, output LED_G, output LED_B);
assign LED_R = SW[0];
assign LED_G = SW[1];
assign LED_B = SW[2];
endmodule
This module directly connects each of the switches in the board to each LED red, LED green, LED blue colors, since this RGB LED can produce a mix of colors based on the combination of these 3 logic levels for a total of 8 different combinations. For this example, only three of these colors are tested in the video. (PWM RGB signals can produce more colors but this method is not used in this introductory demo.)
Other files are needed in the creation of this simple FPGA design. The project file is called leds.json in JSON format is provided here,
leds.json (301.9 KB)
A file called io.pcf will define the PINS used in this project for the Lattice ICE40 UltraPlus Breakout Board
io.pcf (402 Bytes)
# For the iCE40 UltraPlus (iCE40UP5K-QFN) Breakout Board
set_io LED_R 41
set_io LED_G 40
set_io LED_B 39
set_io SW[0] 23
set_io SW[1] 25
set_io SW[2] 34
set_io SW[3] 43
set_io clk 35
# bank 0
set_io IOT_39A 26
set_io IOT_38B 27
set_io IOT_42B 31
set_io IOT_43A 32
set_io IOT_45A_G1 37
set_io IOT_51A 42
set_io IOT_50B 38
#spi
set_io SPI_SS 16
set_io SPI_SCK 15
set_io SPI_MOSI 17
set_io SPI_MISO 14
Not all of these will be used in this demo, only the relevant ones are LED_R, LED_G, LED_B, SW[0], SW[1], SW[2]. The other PINS not used in this demo, are used for bank 0 and the SPI interface. This file can be enhanced to include more definitions as needed.
The first step is to create the project folder with all these files shown below,
digikey_coffee_cup@switch: ls
leds.v
leds.json
io.pcf
Start to process the project with yosys as follows,
digikey_coffee_cup@switch: yosys -p synth_ice40 "-top top -json leds.json" leds.v
this will produce the following output in the Linux terminal,
[00000.000037] /----------------------------------------------------------------------------\
[00000.000043] | |
[00000.000048] | yosys -- Yosys Open SYnthesis Suite |
[00000.000052] | |
[00000.000056] | Copyright (C) 2012 - 2020 Claire Xenia Wolf <claire@yosyshq.com> |
[00000.000059] | |
[00000.000063] | Permission to use, copy, modify, and/or distribute this software for any |
[00000.000067] | purpose with or without fee is hereby granted, provided that the above |
[00000.000071] | copyright notice and this permission notice appear in all copies. |
[00000.000074] | |
[00000.000078] | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
[00000.000081] | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
[00000.000110] | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
[00000.000117] | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
[00000.000121] | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
[00000.000127] | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
[00000.000140] | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
[00000.000146] | |
[00000.000152] \----------------------------------------------------------------------------/
[00000.000156]
[00000.000164] Yosys 0.33 (git sha1 2584903a060)
[00000.000170]
[00000.001164]
[00000.001173] -- Parsing `leds.v' using frontend ` -vlog2k' --
[00000.001269]
[00000.001279] 1. Executing Verilog-2005 frontend: leds.v
[00000.001284] Parsing Verilog input from `leds.v' to AST representation.
[00000.001408] Storing AST representation for module `$abstract\top'.
[00000.001428] Successfully finished Verilog frontend.
[00000.001444]
[00000.001451] -- Running command `synth_ice40' --
[00000.001460]
[00000.001465] 2. Executing SYNTH_ICE40 pass.
[00000.001497]
[00000.001501] 2.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_sim.v
[00000.001506] Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_sim.v' to AST representation.
[00000.013292] Generating RTLIL representation for module `\SB_IO'.
[00000.013424] Generating RTLIL representation for module `\SB_GB_IO'.
[00000.013586] Generating RTLIL representation for module `\SB_GB'.
[00000.013613] Generating RTLIL representation for module `\SB_LUT4'.
[00000.013963] Generating RTLIL representation for module `\SB_CARRY'.
[00000.014145] Generating RTLIL representation for module `\SB_DFF'.
[00000.014329] Generating RTLIL representation for module `\SB_DFFE'.
[00000.014576] Generating RTLIL representation for module `\SB_DFFSR'.
[00000.014914] Generating RTLIL representation for module `\SB_DFFR'.
[00000.015245] Generating RTLIL representation for module `\SB_DFFSS'.
......
etc etc etc
......
Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_map.v
[00000.455808] Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_map.v' to AST representation.
[00000.456112] Generating RTLIL representation for module `\$lut'.
[00000.456328] Successfully finished Verilog frontend.
[00000.456341]
[00000.456344] 2.44.2. Continuing TECHMAP pass.
[00000.456365] No more expansions possible.
[00000.456387] <suppressed ~3 debug messages>
[00000.459356]
[00000.459365] 2.45. Executing AUTONAME pass.
[00000.459978]
[00000.459982] 2.46. Executing HIERARCHY pass (managing design hierarchy).
[00000.459989]
[00000.459993] 2.46.1. Analyzing design hierarchy..
[00000.459996] Top module: \top
[00000.460003]
[00000.460007] 2.46.2. Analyzing design hierarchy..
[00000.460010] Top module: \top
[00000.460016] Removed 0 unused modules.
[00000.460886]
[00000.460891] 2.47. Printing statistics.
[00000.460898]
[00000.460902] === top ===
[00000.460903]
[00000.460907] Number of wires: 4
[00000.460910] Number of wire bits: 7
[00000.460913] Number of public wires: 4
[00000.460918] Number of public wire bits: 7
[00000.460920] Number of memories: 0
[00000.460924] Number of memory bits: 0
[00000.460927] Number of processes: 0
[00000.460930] Number of cells: 0
[00000.460940]
[00000.461566] 2.48. Executing CHECK pass (checking for obvious problems).
[00000.461573] Checking module top...
[00000.461584] Found and reported 0 problems.
[00000.462700]
[00000.462704] -- Writing to `p top -json leds.json' using backend `json' --
[00000.462865]
[00000.462870] 3. Executing JSON backend.
End of script. Logfile hash: 0c9178c87b, CPU: user 0.46s system 0.01s, MEM: 19.25 MB peak
Yosys 0.33 (git sha1 2584903a060)
Time spent: 74% 13x read_verilog (0 sec), 7% 1x synth_ice40 (0 sec), ...
To continue the build process then issue this command that does the FPGA place and route,
digikey_coffee_cup@switch: nextpnr-ice40 --up5k --json leds.json --pcf io.pcf --asc leds.asc
then once it is finished then the terminal will display this,
...
etc.
...
Info: [ 79233, 79271) |
Info: [ 79271, 79309) |
Info: [ 79309, 79347) |
Info: [ 79347, 79385) |
Info: [ 79385, 79423) |
Info: [ 79423, 79461) |*
13 warnings, 0 errors
Info: Program finished normally.
To finish the build process then create the .bin file as follows,
digikey_coffee_cup@switch: icepack leds.asc leds.bin
The FPGA can be programmed to the SRAM as follows
digikey_coffee_cup@switch: iceprog -S leds.bin
or to the FLASH memory,
digikey_coffee_cup@switch: iceprog leds.bin
Make sure the jumpers in J6 on the board are properly configured for each case, see board details below,
Here is a picture on the board that shows the jumper configurations closer,
Once this step is complete then the FPGA is configured. The following video shows this demo,
The video shows that when each button is pressed the corresponding RGB LED lights up. This is an example of a simple “asynchronous” FPGA configuration example.
This introductory chapter has covered the IceStorm FPGA configuration mechanism for this amazing board. In the next chapter we will cover the APIO route to configure the FPGA board. The Lattice ICE40 UltraPlus Breakout Board is a portable, inexpensive, with a prototype area FPGA development board that can be used for many applications and is available at DigiKey. Have a good day!
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